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Data Sheet
NSD-1202
Dual Piezo Motor Driver IC for SQL Series SQUIGGLE Motors
1 General Description
The NSD-1202 is a dedicated piezo motor driver ASIC capable of driving two SQL Series SQUIGGLE motors from a single 2.8 to 5.5 VDC supply. The two motors can be controlled independently using a standard IC interface. An on-chip DC-DC step-up converter generates the high supply voltage (24 to 40 VDC) required by the piezoelectric elements of the SQUIGGLE motor. Four half bridge drivers create pairs of phase-shifted square waves with ultrasonic frequency as required to drive SQL Series SQUIGGLE motors.
2 Key Features
Wide Input Supply Voltage Range: 2.8 to 5.5VDC Step-up converter to generate programmable high-voltage power supply (24 to 40V) Minimum 65% efficiency (at VDD=2.8V, IOUT=25mA, freq=2MHz) 4x output driver with defined rise/fall time IC interface On chip registers store driver instructions Power-down mode for minimal power consumption in stand-by Small 4x4mm 16-Pin QFN Package This part supersedes and is backward-compatible with the NSD1102.
3 Applications
Figure 1. NSD-1202 Functional Block Diagram The NSD-1202 is ideal for SQUIGGLE piezoelectric motor driver.
VIN (2.8-5.5V)
C1 22F
L1 4.7H D1
VDDH (programmable 24V...40V)
C2
VDD (2.8-5.5V) XPD VSS SDA SCL ADR
Voltage reference Step-up controller
LX
VDDH
TRIM
1F
NSD-1202
IC Interface
Registers
VSSP
Levelshifter
1 1
DRV2P1 DRV2P2 DRV1P1 DRV1P2
CLK
LOGIC
Levelshifter Levelshifter Levelshifter
1 1
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Data Sheet - P i n A s s i g n m e n t s
4 Pin Assignments
Figure 2. Pin Assignments (Top View)
DRV2P1
DRV2P2
DRV1P1
14
16
15
DRV1P2
13
VDDH ADR LX VDD
1
12
NC NC VSSP XPD
2
11
NSD-1202
3 10 4 9
5
6
7
8
4.1 Pin Descriptions
Table 1. Pin Descriptions Pin Name VDDH ADR LX VDD VSS CLK SDA SCL
1
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Pin Type Supply pad Digital input Analog I/O Supply pad Digital input Digital I/O Digital input Supply pad Digital I/O
Character Power Input Output Power GND Input BiDir Input GND BiDir High Voltage Supply Slave address input
SDA
VSS
SCL
CLK
Description
Power Output to Inductor Low Voltage Supply Signal Ground 20MHz Clock input Data IO Data clock (400 kHz Max) Power Down, active low Power Ground Test mode pin, connect to VSS Test IO pin, connect to VSS Half Bridge 1 Phase2 Output Half Bridge 1 Phase 1 Output Half Bridge 2 Phase2 Output Half Bridge 2 Phase1 Output
1
XPD VSSP NC11 NC12 DRV1P2 DRV1P1 DRV2P2 DRV2P1
Analog I/O
Output
1. SDA (Data IO) and SCL (Data clock) constitute an IC interface. Both have open drain outputs.
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Data Sheet - A b s o l u t e M a x i m u m R a t i n g s
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 4 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings Symbol VVDD VVDDH VLX VLV Iscr ESD Ptot Rthja Tstrg Parameter Voltage at low voltage supply pin Voltage at high voltage supply pin Voltage at LX pin Voltage at CLK, SDA, SCL, XPD Input current (latchup immunity) Electrostatic discharge Total power dissipation Thermal resistance QFN16 4x4mm Storage temperature 29.7 -40 33 Min -0.3 -0.3 -0.6 -0.3 -50 1 1 36.3 150 Typ Max 7 50 VVDDH+0 .3 7 50 Units V V V V mA kV W K/W C Norm: IPC/JEDEC J-STD-020C. The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/JEDEC J-STD-020C "Moisture/Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices". Low voltage pads Norm: Jedec 78 Norm: MIL 883 E method 3015 Human body model: R=1.5k, C=100pF Comments Internal 3.3V supply (VDDA) High voltage supply
Tbody
Soldering temperature
260
C
Humidity non-condensing
5
85
%
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Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6 Electrical Characteristics
Table 3. Operating Conditions Symbol VVDD VVDDH VLX VVSSP VVSS VLV TAMB Parameter Voltage at VDD Voltage at VDDH Voltage at LX pin Voltage at VSSP Voltage at VSS Voltage at CLK, SDA,SCL, XPD Ambient temperature GND reference for step up converter GND reference potential Low voltage pads Conditions VDD rise time is between 10s and 100ms High voltage supply Min 2.8 24 -0.6 -0.3 0 -0.3 -40 Typ Max 5.5 40 VVDDH +0.3 0.3 0 5.5 85 Units V V V V V V C
6.1 Electrical System Specifications
All system parameters are guaranteed up to 125C junction temperature unless explicitly mentioned. Table 4. Electrical System Specifications Parameter VDD Ambient temperature Junction temperature Stand-by current consumption Operating current consumption Output Voltage (VDDH) Output Voltage (VDDH) steps Output Voltage accuracy Hysteresis Output current DC VIN=2.8V, Efficiency calculations assume the use of the components as specified in the Applications Description section (see page 6) -6 0.325 0.5 XPD=LOW, temp=27C; No activity on IC interface and CLK static XPD=HIGH, Step-up converter on but NOT RUNNING A MOTOR Default value is 35V after start-up 24 0.5 +6 0.675 25 1.5 40 Conditions Min 2.8 -40 -40 Typ 3.3 Max 5.5 +85 +125 5 Units V C C A mA V V % V mA
Efficiency
65
%
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Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6.2 DC/AC Characteristics for Digital Inputs and Outputs
Table 5. CMOS Input: XPD, ADR, CLK Symbol VIH VIL ILEAK CIN Parameter High level input voltage Low level input voltage Input leakage current Capacitive Load Conditions Min 1.2 VSS Typ Max VDD 0.3 1 15 Units V V A pF
Table 6. CMOS IC Interface: SDA, SCL Symbol VIH VIL ILEAK VOH VOL CL RPU SCL Parameter High level input voltage Low level input voltage Input leakage current High level output voltage Low level output voltage Capacitive load: SDA, SCL External pull-up resistor: SDA, SCL IC write frequency As defined by IC spec Maximum clock frequency to write data 1.2 6.0 Depending on external pull-up resistor @3mA output current VVDD -0.5 Conditions Min 1.2 VSS Typ Max VDD 0.3 1 VVDD VSS+0.4 50 7.1 400 Units V V A V V pF k kHz
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Data Sheet - D e t a i l e d D e s c r i p t i o n
7 Detailed Description
Figure 1 shows the main building blocks of the system: Voltage reference Step up converter IC interface Registers Selectable feedback Four (4) half bridge drivers Supplementary blocks such as biasing or power-on reset are not shown. The step-up converter is built as a hysteretic step-up converter. The half bridge drivers operate rail to rail (VSSP to VDDH). User supplied external components C1, C2, L1 and D1 provide voltage boost and regulation. The output voltage can be programmed via the IC interface in 0.5V steps between 24V and 40V. This voltage, along with the duty cycle (or pulse width) of the drive signal, determines the speed of the motor. Registers define the switching frequency of the motor, which can be dynamically adjusted from 140 KHz to 180 KHz for optimum motor performance. Other registers control motor direction and the number of pulses the motor is active (correlating to distance traveled). The XPD input enables a stand-by mode.
7.1 Step Up Converter
The internal switching converter, together with L1 and C2, form a step up DC/DC converter used to create the high level voltage VDDH in the range 24 to 40V. The switch includes an over-current detect circuit to ensure safe operation at all times. The output voltage can be programmed via IC interface in steps of 0.5V from 24V to 40V. At power up the default output voltage is set to 35V.
7.2 IC
The IC interface is used to control the NSD-1202 and set the value of several registers. These registers will define the output voltage (by changing the resistive feedback divider) as well as the direction and duration of the output driver signals. The period count. duty cycle (or pulse width) and pulse count registers can be set separately for each motor. Start/Stop Condition: A HIGH to LOW transition on the SDA line while SCL is HIGH is the start condition for the bus. A LOW to HIGH transition on the SDA line while SCL is HIGH is the stop condition. Every byte put on the SDA line must be 8-bits long. Each byte must be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first. Data transfer with acknowledge is obligatory. The acknowledge-related clock pulse is generated by the master. The receiver must pull down the SDA line during the acknowledge clock pulse. The NSD-1202 is a slave device on the bus. There are two different access modes: - Byte write - Page write The device can be addressed using 7-bit addressing. The first 6 bits are fixed. The last bit can be set via package pin. Provision will be made for data collision due to non-synchronization between the external clock and the internally generated clock.
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Data Sheet - D e t a i l e d D e s c r i p t i o n
7.3 Register Map
The table below shows the registers which can be addressed over the IC interface. Description Period count A Pulse count A (high byte) Period count B Pulse count B (high byte) Output voltage Duty cycle A Duty cycle B Reserved register
1 1
Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 10h X X X X h X X h X
Data Byte MSB X d X X d X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X LSB X X X X X X X X X X
Pulse count A (low byte)
Pulse count B (low byte)
1. The master clock doubling bit (`h') of both registers 01h and 04h must set in order for the doubling to take affect (even if only driving one motor). Do not use clock doubling if the master clock has a frequency > 10 MHz.
7.4 Output Drivers
The output drivers operate rail to rail and are capable of driving a large capacitive load. In power-down mode the output drivers are pulled to ground. The same applies when the motor is off. Symbol Parameter Rise/fall time CLOAD Load capacitance Switching frequency Switching frequency step Switching frequency duty cycle Duty cycle accuracy Phase shift Phase shift error Master clock frequency (CLK) Conditions CLOAD 600pF The load capacitance may be lower than 500pF but the lower the value the shorter the rise time. The accuracy of switching frequency and phase shift will be defined depending on master clock frequency; the given values are for 20MHz master clock. Lower master clock frequencies give higher deviations. For Squiggle applications 20MHz clock is required, 10 MHz can be used with the clock doubling feature. Clock doubling feature may be employed when using a 10MHz or less master clock frequency Min 25 500 140 0.98 1 -1 90 3 1 20 20 Typ 100 600 170 1.45 Max 250 700 180 1.61 50 +1 Units ns pF kHz kHz % % deg deg MHz
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Data Sheet - D e t a i l e d D e s c r i p t i o n
7.5 Period Counter
The period counter is used to define the switching frequency of the motor. The pulse period is generated by dividing the clock input frequency by the given period counter value. The MSB of the high byte of the pulse counter (h) is used to enable the internal frequency doubler. This function should be used only for input clock frequencies of 10MHz or less. At 20MHz input clock a decimal period counter value of 111 gives an output frequency of 180.18 kHz. A period counter value of 112 results in a switching frequency of 178.75 kHz. This is equal to a maximum frequency step of 1.61 kHz. The frequency resolution gets better for lower output frequencies, assuming a fixed input clock frequency. The following table presents examples of the period counter and output switching frequency relationship. The values are given for 20MHz and 10MHz clock input frequency. (At 10MHz the frequency doubler can be activated, which leads to the same results.) Period Counter Value 0110 1111 0111 0000 1000 0101 1000 0110 1000 1110 1000 1111 Typ 180.18 178.57 150.37 149.25 140.85 139.86 Unit kHz kHz kHz kHz kHz kHz
7.6 Pulse Counter
The pulse counter sets the number of pulses the motor should be active. Writing all zeros to the pulse counter stops the motor, even if the previous set counter value is not completed. All outputs are then low. The same is valid for power-down mode. Bit 6 of the high byte in the pulse counter (d) is used to set the direction of motor motion. Pulse Counter Value XXXX X000 0000 0000 XXXX X100 0000 0000 XXXX X111 1111 1111 Typ 0 1024 2047 Unit pulses pulses pulses Maximum possible number of pulses Conditions Motor is off, driver outputs are low
7.7 Output Voltage Register
This register is used to define the output voltage of the boost converter. The register value is directly transferred to the analog part. The default value for this register set during power up or power down (XPD = LOW) is equal to 35V nominal output voltage. Output Voltage Register 0001 0001 0001 0010 0001 1111 0010 0111 0011 0000 0011 0001 Typ 24.0 24.5 31.0 35.0 39.5 40.0 Unit V V V V V V Default value Conditions
Varying the output voltage can be used to vary the speed of the motor. However, if two motors are being driven, both motors use a common output voltage and therefore one setting applies to both motors. To control the speed of two motors independently, use the Duty Cycle Register.
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Data Sheet - D e t a i l e d D e s c r i p t i o n
7.8 Duty Cycle Register
A register is used to define the duty cycle (or pulse width) of the driver output signal for each motor. The register value is directly transferred to the analog part. Since changing the duty cycle will change the speed of the motor, this register can be used to control the speed of two motors independently. (Motor speed can also be controlled by varying the voltage; however, one setting applies to both motors. See the previous section, Output Voltage Register.) To provide motor independent speed control, the duty cycle may be adjusted from 50% (max speed) down to ~12% (minimum speed). A lower duty cycle could be used, but may not provide enough vibration amplitude to overcome the load. The default value for this register set during power up or power down (XPD = LOW) is equal to 00h. In this case the default duty cycle of 50% is generated. The resulting duty cycle and resolution of single steps is depending on the master clock frequency and the switching frequency of the driver output. In the following table an example for 20MHz clock input and 150kHz driver frequency is given. The value of the duty cycle register should not exceed 50% of the period counter value. Duty Cycle Register 0000 0000 0000 0001 0000 1101 0001 1011 0010 1000 0011 0101 0100 0010 0100 0011 Min Typ 49.6/50.4 0.8 9.8 20.3 30.1 39.8 49.6 50.4 Max Unit % % % % % % % %
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Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
8 Application Information
The NSD-1202 is designed to drive two SQL-1.8 SQUIGGLE motors. Recommended external components are as follows: Component C1 C2 L1 D1 Description 22F Cap 6.3V 1F Cap 50V 4.7H Inductance Diode Manufacturer www.murata.com www.coilcraft.com www.nxp.com Part Number GRM21BR60J226ME39 GRM21BR71H105KA12 EPL2014-472 PMEG6010CEJ WxLxH [mm] 1.25x2.0x1.25 1.25x2.0x1.25 2.0x2.0x1.4 1.25x2.5x0.80
New Scale offers a convenient MC-33DB evaluation board which includes these components, along with input and motor connectors, to take full advantage of the NSD-1202 ASIC. The XPD input can be used to place the ASIC in stand-by mode for minimal current consumption when the motor is not moving. Alternatively, the designer can implement an external switch to power off the ASIC completely when the motor is not moving: the SQUIGGLE motor holds its position with the power off.
VIN (2.8-5.5V)
C1 22F
L1 4.7H D1
VDDH (programmable 24V...40V)
C2
VDD (2.8-5.5V) XPD VSS SDA SCL ADR
IC Interface Voltage referenc e Step-up controlle r
LX
VDDH
TRIM
1F
DRV1P1 DRV1P2
NSD-1202
Register s
VSSP
NSD-1202 LevelDual Piezo Motor Driver 1
shifter Levelshifter Levelshifter Levelshifter 1 1 1
DRV2P1 DRV2P2 DRV1P1 DRV1P2
DRV2P1 DRV2P2
CLK
LOGI C
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Data Sheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
9 Package Drawings and Markings
The devices are available in a 16LD QFN (4x4mm) package. Figure 3. 16LD QFN (4x4mm) Package Drawings and Dimensions
5
6
7
8
4
9
3
10
2
11
#1
12
16
15
14
13
Symbol A A1 b D E D2 E2 Notes:
Min 0.75 0.25
2.30 2.30
Nom 0.85 0.203 REF 0.30 4.00 BSC 4.00 BSC 2.40 2.40
Max 0.95 0.35
2.50 2.50
Symbol e L L1 P aaa ccc
Min 0.40
Nom 0.65 BSC 0.50 45 BSC 0.15 0.10
Max 0.60 0.10
1. Dimensioning and tolerancing conform to ASME Y14.5M-1994. 2. All dimensions are in millimeters, angle is in degrees. 3. Dimension b applies to metallized terminal and is measured between 0.25mm and 0.30mm from terminal tip. Dimension L1 represents terminal full back from package edge up to 0.1mm is acceptable. 4. Coplanarity applies to the exposed heat slug as well as the terminal. 5. Radius on terminal is optional.
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Data Sheet - O r d e r i n g I n f o r m a t i o n
10 Ordering Information
The devices are available as the standard products shown in Table 7. Table 7. Ordering Information Ordering Code NSD-1202BQFT Description Dual Piezo Motor Driver IC Delivery Form Tape & Reel Package QFN-16 (4x4mm)
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Data Sheet - C o p y r i g h t s
Copyrights
Copyright (c) 1997-2009, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered (R). All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services.
Contact Information
Headquarters austriamicrosystems AG Tobelbaderstrasse 30 A-8141 Unterpremstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact
Contact Information
New Scale Technologies, Inc. 121 Victor Heights Parkway Victor, NY 14564 Tel: +1 585 924 4450 Fax: +1 585 924 4468 sales@newscaletech.com www.newscaletech.com www.austriamicrosystems.com Revision 0.1 13 - 13

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